The invention relates to a FET storage and more particularly to FET storage with sense latch for increasing the number of dynamic FET storage cells on the bit lines (BL) connected to this sense latch (SL), wherein the storage cells are arranged at the crossing of word lines (WL) and bit line pairs (BL1, BL2) in a multilayer metal semiconductor structure and are connected by addressable bit switches (B/S) to read/write drivers, and wherein one sense latch (SL) is associated with each bit line pair.
Highly integrated capacitive storages and field-effect transistors are known in principle. Thus, for example, German Offenlegungsschrift No. 1,774,482 describes a capacitive word-oriented storage, each of whose cells consists of one field-effect transistor and one capacitor. One node of the transistor is connected to the capacitor, the other to the bit line, the gate electrode to the word line and the substrate node to an operating voltage source. Such a single transistor storage cell consisting of field-effect transistors has the advantage that its integration density is high and its manufacturing process relatively simple.
However, the main disadvantage of such a single FET storage cell is that information is read or written relatively slowly. Apart from this, the read signal is relatively small and the capacitive load of the bit and word lines relatively high. As the packing density of such storages increases, serious problems are encountered in so far as during reading or sensing the contents of a storage cell the signal is no longer discernibly small. This necessitates extremely complicated sense circuits on the one hand and very strict observance of the times and levels of a number of successive control signals on the other. The signal sequence for a read operation differs from that for a write operation, so that such a storage requires many peripheral circuits for its operation. At the same time, the operating speed declines as the magnitude of the sensed signal decreases.
To achieve faster read/write cycles, integrated dynamic semiconductor storages with cells of two field-effect transistors have been developed. Such a storage with two storage capacitors, each accessible by one field-effect transistor, is known from IBM Technical Disclosure Bulletin, Vol. 18, No. 3, August 1975, pp. 786 and 787, and German Pat. No. 2,431,079. According to this material, each storage cell consists of two series circuits with one storage capacitor and one read/write field-effect transistor each. These series circuits are arranged between the bit lines of a bit line pair and a common AC grounded node. A common word line links the control electrodes of the two transistors. When the information of an addressed storage cell is read, the difference signal on both bit lines is fed to a latch for amplification. This circuit arrangement ensures a high read/write speed with a relatively simple control signal sequence. However, an essential disadvantage is that the number of storage cells for each bit line is limited, as otherwise the capacitive load would become too great, so that the storage cell size, the line width or the peripheral circuits would be increased considerably or the read signal would become so small that it could no longer be reliably sensed without excessive means.
To further improve the speed and to simplify the time control, German Pat. No. 2,712,735 provides for the early selection of the bit line switches, necessary for linking the storage cell area and the data input/output lines, to be effected by a low control pulse, so that as a function of the difference signal occurring, which is preferably preamplified and applied to the appertaining bit line pair by a storage cell, the switching threshold of only one of the two bit line switches is exceeded, while the bit line switch in the other bit line remains latched, preventing the potential of that bit line, and thus the potential of the cell node connected thereto, from dropping. A further reduction in the access time by reducing the time for sensing the stored values is not attainable without difficulties, as in such a case the information could no longer be reliably sensed and a signal that has been too strongly reduced would necessitate a low speed anyhow. Apart from this, the number of cells for each bit line is limited by the capacitive loads.
A 64K-bit MOS dynamic RAM is described in IEEE, Journal of SCC, pp. 184 to 189, of April 1980 under the title "A 64 Kilobit Dynamic RAM" by F. Smith et al. This storage, too, has the disadvantage that the number of cells for each bit line is limited by the capacitive load. If the number of storage cells for each bit line were to be increased considerably, the higher detrimental capacities of such a storage would have to be compensated for by higher currents, wider lines and more complicated peripheral circuits.
Therefore, it is the object of the invention to provide a storage with cells of field-effect transistors, wherein one latch is common to the bit lines and the number of storage cells persense latch can be doubled, without increasing the storage cell size or line width and without the peripheral circuits being subjected to critical technical requirements.